Blog: Jim Lewis Blog – OSVVM gone Apache … on the path to IEEE Open Source

VHDL’s adventure started with IEEE Open Source started with a pilot program for releasing the IEEE std 1076-2019 (VHDL LRM) packages as open source.
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In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license.  This is being done in preparation to migrate OSVVM to IEEE Open Source.

In the fall of 2019, OSVVM was accepted as another pilot program for IEEE Open Source.

Why is IEEE going into Open Source?  Just like IEEE standards, IEEE Open Source projects like OSVVM align well with IEEE’s mission statement, “IEEE’s core purpose is to foster technological innovation and excellence for the benefit of humanity.”

Why is OSVVM going to IEEE Open Source?  OSVVM is currently a small team of like minded individuals. We would like to attract a larger set of people to the project.  IEEE’s reputation and backing will help.  To facilitate accepting contributions from a larger audience, IEEE is also providing support with collecting and tracking contributor license agreements (CLA) for individuals and organisations.

Currently OSVVM is available on GitHub at: https://github.com/OSVVM.

Sometime in Q1 we will moving the official release to IEEE Open Source servers.  At that time we will also do an announcement inviting potential OSVVM developers to join us.

About OSVVM

Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries.  Using these libraries one can create a simple, readable, and powerful testbench that is suitable for either a simple FPGA block or a complex ASIC.

According to the 2018 Wilson Verification Survey , OSVVM is the

• #1 VHDL Verification Library
• #1 FPGA Verification Library in Europe (ahead of SystemVerilog)

The OSVVM utility library offers the same capabilities as those provided by other verification languages (such as SystemVerilog and UVM):

• Transaction-Level Modelling
• Constrained Random test generation
• Functional Coverage with hooks for UCIS coverage database integration
• Intelligent Coverage Random test generation
• Utilities for testbench process synchronisation generation
• Utilities for clock and reset generation
• Transcript files
• Error logging and reporting – Alerts and Affirmations
• Message filtering – Logs
• Scoreboards and FIFOs (data structures for verification)
• Memory models

The OSVVM model library provides the following models. The models all use records for the transaction interfaces, so connecting them in a testbench only requires a single signal.

• AXI4 Lite Master
• AXI4 Lite Slave transaction model
• AXI Stream Master
• AXI Stream Slave
• UART Transmitter
• UART Receiver (with error injection)

Testbenches for each model are in the Git repository, so you can run a simulation and see a live example of how to use the models.

Getting Started with OSVVM

The fastest way to get started with OSVVM is SynthWorks’ Advanced VHDL Testbenches and Verification .