Archive
Blog: Achieving Better Coverage with VHDL – Part 3
In the final part of this series we look at smart functional coverage and how to accomplish it with the Open Source VHDL Verification Methodology...
17 August, 2020
Blog: Do you think in pictures?
This blog explains the benefits of design from using Aldec's Active-HDL....
10 August, 2020
Blog: Better to be safe than sorry
This blog talks about connectivity through technology and devices....
27 July, 2020
Blog: Automation in UVM Register Modelling
In this blog, Nomita provides insight into communications between hardware and software for UVM verification engineering....
20 July, 2020
Blog: Achieving Better Coverage with VHDL – Part 2
In this part two of our three-part series, we will take a look at property coverage, covering the basic terms along with a design example....
13 July, 2020
Blog: A snake in the computer
This blog explains the installation of Python 3.8 and OSVVM for Riviera-PRO....
08 July, 2020
Blog: Updating the OSVVM Library in Riviera-PRO
This blog explains the installation of Python 3.8 and OSVVM for Riviera-PRO....
07 July, 2020
Blog: Strange days indeed
this blog mentions how all of our VHDL training courses are offered online, and benefit from access to the instructor....
06 July, 2020