The Next Generation of Register, Sequence, and SoC Automation - FirstEDA
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The Next Generation of Register, Sequence, and SoC Automation

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate design RTL, UVM testbench models for simulation, and user documentation for the registers in your design. This saves your development teams weeks of time, especially when the design evolves and register changes can be propagated across the project with a specification update and the simple push of a button. IDesignSpec (IDS) remains our best-known and most widely adopted product.

 

We expanded our solutions to include the sequences to access and program your registers with ISequenceSpec (ISS). We automatically generate sequences for various types of register behavior, including access to individual fields within registers. This is highly valuable for your chip verification team. We also help your driver and firmware developers by generating C code to access and program the registers in the actual fabricated chip as well as in hardware-software co-simulation and emulation. Like IDS, ISS also generates documentation in several formats.

 

We extended our UVM support with the Automatic Register Verification (ARV) add-on to IDS. ARV generates a complete verification environment for automatically verifying all your addressable registers across all access types. We create the complete UVM testbench: bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences, and the verification plan. This testbench leverages the UVM register models generated by IDS. ARV also generates C code for driver development, interfaces with Portable Stimulus Standard (PSS) models, and supports formal verification.