Technical Article: Prefix all signals in an instantiation - FirstEDA
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Technical Article: Prefix all signals in an instantiation

Posted on 11-10-2019 by Bart Brosens

 

 

When you auto-complete an instantiation using the Sigasi Studio Content Assist, wire or signal names in the port map get a default value which is equal to the port name. In many designs this can be a insufficient. You might need to give the wires/signals in the portmap a prefix so they match the actual wire/signal names in the design.

 

Updating all wires or signals in a long port map can be a tedious task. However, using the Regular expressions capability of the Find/Replace dialog, pre-pending the prefix to the wires/signals can be done more efficient.

 

Find and Replace using regular expressions

 

In the screenshot, the Find field contains \((.*)\) to select everything between brackets. The outer brackets are escaped to match the actual brackets in the port map. The inner brackets capture the text between the brackets, which is back referenced with \1 in the Replace with field. More information on this regular expression can be found in the Java regex tutorial.