Release: Aldec at DVCon Europe: Demonstrating a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning software - FirstEDA
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Release: Aldec at DVCon Europe: Demonstrating a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning software

Date: Oct 21, 2019

 

Henderson, NV, USA – October 21, 2019– Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, is exhibiting at DVCon Europe (October 29-30, Munich, Germany) and will be demonstrating a powerful hybrid co-emulation platform for large ASIC and SOC designs.

 

The platform was created using an Aldec HES-US-440 hardware emulation system and an Aldec TySOM-3 embedded system board, where the latter features a Xilinx Zynq Ultrascale+ FPGA which contains a quad-core ARM Cortex-A53. An FMC Host2Host bridge between the two Aldec products allows the TySOM board to share the ARM cores with the HES, meaning the software team members can prototype on fast clock-speed hardware and benefit from fast system boot-up (minutes instead of hours).

 

Aldec will also be showcasing the recently introduced automatic FPGA partitioning feature of its popular HES-DVM tool; the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs. Traditionally, and subject to design complexity and constraints, the manual partitioning of multiple FPGAs used for prototyping can take days, or even weeks, whereas HES-DVM can perform the task in minutes.

 

“We’re at DVCon Europe with solutions that epitomise what EDA is all about, and how automation can save hardware and software teams considerable amounts of time, while providing them with confidence in their designs,” comments Krzysztof (Chris) Szczur, an Aldec Hardware Verification Products Manager and who will be on booth #405 for both days of DVCon Europe.

 

In addition, Aldec will be using DVCon Europe to showcase the latest features in Active-HDL, the Windows based integrated FPGA design creation and simulation solution and which includes a full HDL and graphical design tool suite and an RTL/gate-level mixed-language simulator.

 

Aldec will also be previewing many yet-to-be announced features scheduled for inclusion in the next release of Riviera-PRO, the company’s popular advanced verification platform which includes support for the latest verification libraries (of UVM, for example) and simulation optimisation algorithms for achieving the highest performance in VHDL, Verilog, SystemVerilog, SystemC, and mixed-language simulations.