[vc_row][vc_column width="1/6"][vc_single_image image="18719" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]Formal verification technology appears in the ascendant at the moment. It’s been around forever, it seems, but it’s now...
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms — THURSDAY 9 JULY - 14:00-15:00 BST (15:00-16:00 CEST) Presented by...
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]These days, verification of the most complex designs is performed using a standard verification methodology, probably SystemVerilog-based UVM. Many...
[vc_row][vc_column width="1/6"][vc_single_image image="18719" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]David Kelf, Vice President of Marketing at OneSpin Solutions talks about how as FPGAs have become larger and more...
[vc_row][vc_column width="1/6"][vc_single_image image="21937" border_color="grey" img_link_large="" img_link_target="_self"][vc_column_text]Alex Grove FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]Discover why designs teams are increasingly seeing the value of running equivalence checking during FPGA development to rapidly...
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="21937" qode_css_animation=""][vc_column_text]Alex Grove FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]Why we should continue to leverage ASIC methodology solutions during FPGA development — A few...
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]With Intelligent Coverage, OSVVM offers a built-in VHDL-based, testbench solution. Best of all, OSVVM is free and works in all...
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="19390" qode_css_animation=""][vc_column_text]David Clift FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text el_class="cus-links"]OSVVM continues to develop through community feedback and deployment — If you are...
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]EE Times Blog: Doug Amos, FPGA Consultant — Scalable FPGA-based verification has become a serious alternative to big-box emulation. Did you...
[vc_row][vc_column width="1/6"][vc_single_image image="18717" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]Discover why design teams are recognising the value of standardising on this class-leading Eclipse-based IDE for VHDL development — WEDNESDAY...