EE Times Blog: Doug Amos, FPGA Consultant
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Scalable FPGA-based verification has become a serious alternative to big-box emulation.
Did you see the news?
Aldec is adopting Xilinx Virtex UltraScale devices in its seventh-generation Hardware Emulation Solution, HES-7, thereby heralding a great leap in the capability of FPGA-based verification. There’s more detail in this press release from whence you can also download the technical specification.
Now read on…
Big SoCs
Articles often start with introductory statements of the blindingly obvious, so here’s mine: “Today’s SoCs are big and complex and it takes a long time to verify them.” Ok, that’s understood. Now, what can we do about it?
Well, emulation would sure help shorten those verification run times, wouldn’t it? Just think what you could achieve by running your simulations thousands of times faster. Hmmmm… it’s a pity about the price tag on that emulator, though (they’re not called “big-box” emulators for nothing).
What if you could get that valuable emulator speed-up, but without the capital and operating expense associated with the big-box? What if that came from a company with a 30-year experience in verification EDA, rather than just another FPGA board-maker with a couple of scripts, a transactor, and a big marketing budget?
Well, this column is here to tell you that the scale of the latest FPGA technology is making that possible; also that scalable FPGA-based verification has become a serious alternative to big-box emulation.