Archive

[vc_row][vc_column width="1/6"][vc_single_image image="18719" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]Online Resource Designed to Serve Formal Verification Engineering Community — FormalWorld.org, an online community dedicated to advancing the widespread...

01 March, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="22089" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]From: [ Jim Hogan of Vista Ventures LLC ] Subject: Where Formal ABV whomps HDL simulation for chip verification   Hi,...

01 March, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]by Don Dingee   FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development...

29 February, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="22094" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]From: Raik Brinkmann, CEO OneSpin Solutions   Hi, John   I'm taking a risk here.  Although Jim Hogan is on my Board...

29 February, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="18719" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]Sigasi Leverages OneSpin Solutions LaunchPad Technology to Integrate Formal Code Inspection into HDL Authoring Environment Enables Early Bug Detection...

26 February, 2016

[vc_row][vc_column width="1/6"][vc_column_text] [/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%? by Brian Bailey   There have been a number of times...

02 February, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="21937" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]Reprogrammable, reprogrammable, reprogrammable: What’s great about FPGAs! Blog by Alex Grove, Application Specialist at FirstEDA — I like FPGAs. My...

01 February, 2016

[vc_row][vc_column width="1/6"][vc_column_text] [/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]The potential, and the pitfalls, to making this acquisition work. by Ed Sperling   Intel completed its $16.7 billion acquisition of Altera this week, wrapping up...

04 January, 2016

[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]So, you’re STILL not using UVM? Maybe you’ve taken a good look and decided that the Universal Verification Methodology...

04 December, 2015