by Don Dingee
FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.
Faster host interfaces deliver dual benefits in FPGA-based prototyping. First is the FPGA configuration itself – to program a huge Xilinx FPGA (or more than one) means shipping a large file from the host down to the prototyping hardware. Second is at run time, where co-simulation runs on the host using transactors to control hardware execution in FPGAs. This hybrid solution allows users to run familiar visualization tools at much greater speeds than possible with host-based simulation alone, enabling more extensive verification testing.
What bus should be used to do that? In the not-too-distant past, people were turning to proprietary interfaces to the FPGA-based prototyping system, but those days are over. PCIe is ubiquitous in modern PC platforms and offers plenty of throughput in wider link widths. PCIe IP now widely available in FPGA form thanks to efforts from Xilinx, PLDA, CAST, and others. In some cases, where the SoC design is intended to run on PCIe, that interface might be carried through directly into the FPGAs on the prototyping platform.