Aldec announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017.01, a unified framework...
Continued success is driving growth and territory expansion. We are immediately adding France, Spain & Belgium to our territory and are putting a new sales...
Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary...
Some time ago a marketing person told me that I had better learn SystemVerilog and UVM, otherwise within a year I would be looking for...
Aldec today announces the latest release of its requirements lifecycle management solutions for FPGAs/SoCs, Spec-TRACER™ 2016.12. This release provides industry-proven certification document templates and review...
GOTHENBURG, MARCH 6-10. Why consider moving away from VHDL when it comes to verification? VHDL verification methodologies can be equally as capable as those using...
In this FirstEDA video, Dave Kelf, VP Marking at OneSpin Solutions, discusses with us the subject of functional safety and formal verification....
Aldec announced today that they will present the spectrum of pre-silicon verification solutions at the DVCon Europe Conference and Exhibition to be held October 19-20,...
As with so many EDA products that are now in mainstream use in FPGA design & verification, their early roots were in the ASIC flow....
When I was at Atrenta, we always thought it would be great to do as-you-type RTL linting. It’s the natural use model for anyone used...