PR: Hardware Safety Metrics for ISO 26262 Compliance
Automotive safety engineers know how hard it is to comply with the requirements of ISO 26262. Safety requirements, in turn, create new tasks for hardware...
23 October, 2018
Archive
Article: Visible Benefits
Aldec makes available a ‘4k Ultra HD image pass through’ reference design for users of its Xilinx® Zynq® UltraScale+™ MPSoC embedded development kit TySOM-3-ZU7EV....
16 October, 2018
Article: Domain Crossing Nightmares
Initially, designers had to consider clock domain crossings (CDC). Then reset became an issue, and now designs have increasing numbers of power domains. Every time...
09 October, 2018
WP: Clock Domain Crossings in the FPGA World
Clock domain crossing (CDC) issues cause significant amount of failures in ASIC and FPGA devices. As FPGA complexity and performance grows, the influence of CDC...
07 March, 2018
Blog: FirstEDA Verification Series – Code Coverage
As an important step in a metric driven verification process, code coverage provides a structural level check on the effectiveness of your tests. By collecting...
01 December, 2017
Article: Emulation in FPGA
For many years, emulators were available only to verification teams working on the largest projects in companies with deep enough pockets. Due to size rather...
27 November, 2017
Live Webinar: Boost VHDL Development Time with Background Design Rule Checking
Design rule checking (DRC) is a battle-proven method to improve the quality of digital designs. In safety-critical design processes, such as DO-254, applying design rule...
24 November, 2017
Article: Which Verification Engine?
Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements....
02 November, 2017
Article: Code Coverage within the HDL Editor – now that’s a nice feature
For a long time I have been a fan of code coverage tools that are embedded into the simulators themselves, and which give you the...
21 October, 2017
Blog: My “Advanced VHDL Testbenches & Verification” training experience
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="22548" qode_css_animation=""][vc_column_text]Kevin Nugent FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]With all the hype surrounding competing verification methodologies, it's time for a cool...
14 October, 2017