OSVVM: The #1 VHDL Verification Library - FirstEDA
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OSVVM: The #1 VHDL Verification Library

Blog by Jim Lewis, VHDL Verification Specialist, OSVVM author, VHDL Trainer, Synthworks


Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.


While your EDA vendor may have told you that only enthusiasts use VHDL for verification, the survey results report that OSVVM is used as the FPGA Verification Library for 17% of world wide market.  According to the survey results, as an FPGA verification library,

  • OSVVM is the number 1 VHDL verification library.
  • OSVVM is second only to SystemVerilog’s UVM library.
  • OSVVM is used more than the OVM and AVM SystemVerilog libraries.