Blog by Jim Lewis, VHDL Verification Specialist, OSVVM author, VHDL Trainer
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Some time ago a marketing person told me that I had better learn SystemVerilog and UVM, otherwise within a year I would be looking for a new job! Well, after taking a good look, I decided I would rather teach yoga than use SystemVerilog or UVM – which to me is like the new COBOL. It is now more than 10 years later and I am still happily working with VHDL for FPGA and ASIC design.
For verification I use VHDL, plus OSVVM (Open Source VHDL Verificaiton Methodology). OSVVM is proving to be a popular alternative to SystemVerilog and UVM, now with a community membership of over 1800 (see osvvm.org). With OSVVM you get an ASIC level VHDL verification methodology that is simple enough to use on FPGA projects without having to learn a new language, or the requirement to invest in expensive specialist tools.