FirstEDA Blog – Optimising FPGA Development: From Design to Verification

Field-programmable gate Arrays (FPGAs) have become indispensable in modern electronic systems, providing flexible hardware solutions across various industries.

However, FPGA development often faces challenges such as complexity, scalability, and aggressive timescales. This blog post outlines methodologies, tools, and best practices to optimise FPGA development, ensuring functional correctness and improved performance.

Understanding the FPGA Development Lifecycle

FPGA development typically encompasses several critical stages:

• Design
• Implementation
• Verification
• Validation
• Bring-up Tests
• Integration Tests

Each stage presents potential bottlenecks, including limited resources and specialised tools, and requires personnel with the required skills and knowledge.

Key Methodologies for Optimising FPGA Development

To overcome development bottlenecks and streamline the workflow, the following methodologies are recommended:

1. Increasing the Level of Design Abstraction

Leveraging higher abstraction levels in design processes simplifies complex tasks, promotes design reusability, and facilitates more manageable maintenance and updates.

2. Modular Design and Reusability

Designing FPGA systems modularly allows easier testing, troubleshooting, and code reuse. It enhances clarity and reduces the development cycle time.

3. Simulation and Verification

Effective simulation and design rule-checking (linting) techniques and methodologies ensure design correctness early in development, minimizing costly downstream corrections.

4. Test Reuse

Reusing test scenarios across different stages can improve verification by catching errors early and ensuring comprehensive test coverage.

5. Automation and Version Control

Implementing automation for repetitive tasks and version control systems, such as Git, greatly improves efficiency, reduces errors, and enhances collaboration.

I have been discussing these improvements for the last 20 years, and the FPGA design landscape is constantly evolving. We have seen a move from schematic capture of designs to the use of HDLs and synthesis. This is now moving in some places to use software languages like C, C++ and Python to describe FPGA designs. This move to ever higher levels of abstraction will continue, and with the move to AI-assisted design, I can see a time when we will move away from HDLs to describing our designs at the AI prompt level, even possibly reaching the point where the EDA tools will read our natural language design specifications and generate bit-streams directly from that.

We have been breaking our designs into reusable modular blocks for several years, and this is now moving into our verification environments. We are seeing the adoption of reusable verification IP and bus functional models along with reusable sequences of test vectors. Again, verification will not escape the deft hand of AI, with AI being used to generate test sequences from our design specifications or to suggest test sequences to fill coverage holes.

Tools for FPGA Design

Today, there are many choices for design tools, not just from the many EDA vendors in the marketplace; open-source alternatives have now joined these commercial offerings.

Commercial Tools

Notable commercial tools include:

• Aldec Riviera-PRO
• AMD Vivado
• Synopsys Synplify

Commercial tools provide comprehensive features, vendor support, regular updates, and capabilities suited to high-reliability and safety-critical applications. However, they come with higher initial and ongoing costs.

Open-Source Tools

Popular open-source tools include:

• GHDL
• Verilator
• VS Codium / VS Code
• FuseSoC

Some open-source tools are competitors to commercial ones, while others bring new functionality to the FPGA design flow. These tools are cost-effective and backed by strong community support but can have limitations such as minimal VHDL support, fewer features, and limited debugging capabilities. Another thing to bear in mind is that open-source tools may have a limited number of people working on them, updating code and testing new releases, so fixes may take a long time to appear. However, being open source, you could always attempt to fix a problem or add a new feature yourself.

In this situation, you must ask yourself: Do I understand the software sufficiently to make the change? Do I have the time to make the change, and is this the best use of my time? A potential alternative to this is paying the project maintainer to update the tool to your requirements.

However, many restrictions and limitations may affect your deployment of open-source tools within your FPGA Design environment. Important things to consider, especially when using open-source simulation and verification tools:

• Do I need to use mixed VHDL and SystemVerilog entities/modules?
• Do I need to run code coverage?
• Do I need to use encrypted IP?

Any one of these will prevent you from using those tools. Some can be worked around. For example, we have customers who only use VHDL and write all their own IP, but this is costly in terms of time and money. However, in certain market segments, having full control of your design’s HDL is a definite benefit.

Verification Frameworks

Effective verification is essential to successful FPGA development. Several frameworks enhance this process:

• OSVVM: Provides a structured testbench framework, functional coverage, and constrained random testing and is supported by a range of VHDL verification IPs (VIP)
• UVVM: Features a comprehensive utility library and advanced verification methods, including randomisation and error injection
• Cocotb: Enables Python-based co-simulation, simplifying test creation and integration with automated test discovery and execution
• VUnit: Supports parallel test execution, HDL utility libraries, and automatic test scanning, improving verification efficiency significantly
• UVM: A standardises test methodology and the de facto standard for ASIC verification. With its mix of both class and instance-based instantiation, being productive with UVM can take longer than with other methodologies

Select a verification methodology early in the project, it is crucial to ensure you understand how to get the best from it. This may involve attending training or running a trial project. You also need to know how extensible your verification methodology is because it is almost certain that your next project will be either bigger or more complex, probably both.

All the verification methodologies here have pros and cons, but discussing them all in detail is beyond the scope of this blog post.

Continuous Integration (CI)

Adopting CI methodologies significantly accelerates FPGA development by automating frequent testing and integrating code continuously. Key CI tools include:

• Jenkins
• GitLab
• Bamboo
• Docker

CI ensures issues are caught early, reducing overall development cycles. However, for this to be effective, the FPGA development team must be able to submit their work easily, so having CI run as a post-commit hook is a great idea.

Challenges and Future Trends

FPGA design faces ongoing challenges, such as increasing complexity, the need for scalability, and stringent timescale reductions. Emerging trends indicate a growing role for AI and ML acceleration and an increased use of cloud-based tools. The future also suggests a potential shift towards languages with higher abstraction levels, such as C/C++ or Python, possibly moving away from traditional HDL languages altogether with AI creating our designs from our written ideas.

Conclusion

Optimising FPGA development involves adopting higher design abstractions, modularity, automation, test-driven strategies, effective verification frameworks, and continuous integration practices. While commercial tools offer extensive capabilities, open-source alternatives provide viable solutions under specific circumstances. By understanding these methodologies and tools, developers can navigate FPGA development challenges effectively and enhance their workflow efficiency.

As we see the boundaries between software and hardware blur even more in our FPGAs, our approach to design and the mix of tools we use will inevitably change. AI and ML will take an ever-increasing role in our design and verification in the next few years. Possibly, the next step will be a move toward test-driven design and, from here, using AI to create a hardware design that responds correctly to our tests. We are seeing more AI in our everyday lives, not just ChatGPT or Copilot, and from the tests I have run, it is getting better, but the critical thing is to verify the results as it frequently gets it wrong.

As the old Russian proverb says, “doveryai, no proveryai”. (“trust but verify”).

If you are contemplating your next FPGA design, looking for advanced FPGA development tools, or need VHDL or verification training, why not speak to us at FirstEDA Limited?