Article: Service Revenue Growing With Chip Complexity - FirstEDA
23117
portfolio_page-template-default,single,single-portfolio_page,postid-23117,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-6.0.5,vc_responsive

Article: Service Revenue Growing With Chip Complexity

November 4th, 2019 – By: Ann Steffora Mutschler

 

 

Demand for outside expertise grows with new markets and architectures.

 

 

Rising complexity, new markets, and a shortage of in-house expertise are beginning to rekindle demand for services for the first time in nearly a decade.

 

The semiconductor industry has been racing to design chips for a variety of new and existing applications, but they are facing challenges on a number of fronts:

 

  • Leading-edge chips require new architectures due to a sharp reduction in scaling benefits, sometimes requiring navigating through a variety of advanced packaging and power management schemes with which chipmakers have little experience.
  • Many of these designs are targeted at markets that are still in flux, such as AI and automotive, making it far more difficult to optimise them for power, performance and area, as well as changes in algorithms and industry standards, without the necessary domain expertise.
  • Time-to-market demands require more effective use of multiple tools to deal with multi-physics and changes in the design flow, as well as complex third-party IP that needs to be fully qualified and integrated into designs. Many companies do not have this kind of expertise in-house, or the budgets to compete against large system houses to hire experts across a variety of disciplines.

 

“The SoC design environment is getting very complex,” said Farzad Zarrinfar, managing director, IP division at Mentor, a Siemens Business. “People are creating SoC designs, they put a software layer on top of that, they must create an early prototype, then verify before they go to high volume. All of that integration and complexity needs to be verified at the chip level and the system level.”