Article: Verification Challenges for RISC-V Adoption - FirstEDA
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Article: Verification Challenges for RISC-V Adoption

By Tom Anderson, Technical Marketing Consultant, OneSpin Solutions

 

 

Just a few years ago, the idea of an open-specification processor architecture with open-source implementations available would have been dismissed by many. Modern processor designs are highly complex, with such advanced features as multi-stage pipelines, multi-level caches, out-of-order execution, branch prediction, and memory pre-fetching. Beyond the hardware design, a huge ecosystem is needed. Reference design kits and software development platforms are essential. Operating systems and applications must be ported to the new architecture. A significant portion of the system-on-chip (SoC) industry must design-in the new processor and validate it in silicon. These challenges have appeared daunting indeed.

 

However, the introduction of the RISC-V architecture has defied conventional wisdom and is starting to disrupt the processor world. The original design was developed in the EECS Department at the University of California, Berkeley. The instruction set architecture (ISA), the primary processor specification, is now supported by the RISC-V Foundation. Its more than 200 members span semiconductors, systems, intellectual property (IP), software, academia, and more. Clearly there is a great deal of interest in this topic, but the industry has moved well beyond just curiosity. Many RISC-V cores, and even some SoCs built around these cores, are available as open source. Commercial cores also exist, and chips containing RISC-V processors are shipping. Many software titles have already been ported.