Article: IP Requires System Context At 6/5/3nm - FirstEDA
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Article: IP Requires System Context At 6/5/3nm

May 1st, 2019 – By: Ann Steffora Mutschler

 

At each new process node, gates are free. That opens the door to a lot more IP blocks, and a lot of new challenges.

 

Driven by each successive generation of semiconductor manufacturing technology, complexity has reached dizzying levels. Every part of the design, verification and manufacturing is more complicated and intense the more transistors are able to be packed onto a die. For these reasons, the entire system must be taken into consideration as a whole – not just as individual building blocks as could be done in the past.