Henderson, NV – June 24, 2020 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has added VHDL-2019 feature support and a UVM Registers window to Riviera-PRO, the company’s popular, high performance simulation and debugging tool.
The VHDL-2019 features supported are: Interfaces; Conditional Compilation; Shared Variables on Entity Interfaces; API for Assert (without PSL); API for Calling Path Information (in debug mode); Conditional Expression; and API to access Date, Time and File System.
“Since the ratification of VHDL-2019 as IEEE Std 1076-2019, we’ve been keen to give our users access to as many of the language’s new features as possible,” comments Sunil Sahoo, SW Product Manager.