VHDL 2019: Interfaces

This is the second article in our series about VHDL 2019. In this article we look at the new ability to cleanly express interfaces. You can read the first part here.



VHDL Interfaces


Interfaces are a central element in hardware design. There are many standardized interfaces like I²C, AXI or VGA and every design also has internally designed interfaces to connect various parts of a system. Unfortunately, these interfaces are cumbersome to model using VHDL. Typically, they are not explicitly defined. Instead their description is repeated on every entity. The only way to identify them is through some naming convention, e.g. all ports of the slave AXI interface could be prefixed with slave_axi_0_.


This approach has many drawbacks. Since there is no centralized definition and the solution relies on naming conventions, it can be hard to identify the interface in complex entities. It is also hard to document an interface without a central definition. The interface is not only repeated for every entity that uses it, but also in every instantiation. All this duplicated code is very cumbersome to maintain. For example, changing the type or name of an element of the interface requires edits in many files, even in architectures that just pass the interface to an instantiation. This situation is unacceptable for a language that highly values strong typing and early bug detection; language level support for interfaces is needed.