With Intelligent Coverage, OSVVM offers a built-in VHDL-based, testbench solution. Best of all, OSVVM
is free and works in all Aldec VHDL simulators
—
THURSDAY 25 JUNE – 14:00-15:00 BST (15:00-16:00 CEST)
Presented by Jim Lewis, SynthWorks VHDL Training Expert
—
Open Source VHDL Verification Methodology (OSVVM) is a comprehensive, advanced VHDL verification methodology. Like UVM, OSVVM is a library of free, open-source code (packages). OSVVM uses this library to implement functional coverage, constrained random tests, and Intelligent Coverage random tests with a conciseness, simplicity and capability that rivals other verification languages.
In 2015, OSVVM has added comprehensive error and message reporting (January, 2015.01) and memory modeling (June, 2015.06). With this expanded capability, this presentation takes a look at the big picture methodology progressing transactions to randomization to functional coverage to intelligent coverage to alerts (error reporting) and logs (message reporting) to memory modeling.
Worried about keeping up with the latest trends in verification?
With Intelligent Coverage, OSVVM has a portable, VHDL-based, intelligent testbench solution built into the library. While Accellera is still working on their Intelligent testbench based portable stimulus solution (in the Portable Stimulus Working Group -PSWG), for OSVVM it is already here. Best of all, OSVVM is free and works in VHDL/mixed-language configurations of Aldec Riviera-PRO™ and Active-HDL™ simulators.