Here are some highlight’s from the latest release of Aldec’s mixed-language, FPGA design platform:
Simulation & Debugging:
• Simulation time improvement for designs using VHDL/Verilog Altera Avalon® bus functional models
• Up to 15% less memory consumption on Verilog RTL designs
• Enhancements made to VHDL-2008 and SystemVerilog (Design Constructs)
Design Creation:
• New Net Properties dialog box that allows group operation on wire, bus, composite type, global connector, terminal, or compound bus in block diagram editor
Code Coverage:
• Support for test ranking of coverage results in UCIS-compatible Aldec Coverage Database(ACDB)
• Separate category for ACDB Coverage to allow setting options related to the compilation and collection of coverage data to an ACDB database
Assertions:
• Enhanced assertion messages with assertion cause info that shows the expression in the assertion formula, which cause the assertion failure
Design Flow Manager:
• Xilinx Vivado 2014.04
• Altera™ Quartus II 14.1 Synthesis & Implementation
• Lattice™ Diamond LSE 3.4
• Actel™/Microsemi Designer 11.5
Installation:
• Updated Open Source VHDL Verification Methodology Library(OSVVM) to version 2015.01
• Updated MinGW package – with gcc 4.8.4 & gdb 7.8.1 version
About Active-HDL™
Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.