FPGA Network: “What Next After Flicking The Switch?”
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FirstEDA’s Alex Grove is presenting “Who’s Bug Is It? – The Elusive Systemic Error”.
So, we’ve got that great design entered into the tools and it’s verified and passing though P&R without timing errors. Everything is running to schedule but now comes the really exciting part. We get to download our design into a live FPGA. We release Reset and hold our breath.
Now what?
There may well be as many different approaches to bringing up and debugging designs In-Lab and In-the-Field as there are FPGA design teams. Each of those approaches may use a different combination of tools on the bench and each has its own advantages, but probably also has areas that could be improved. By pooling our experiences in the NMI FPGA Network, we can each learn some new best-practises and accelerate this somewhat unpredictable stage of our FPGA projects.
FirstEDA has been a member of NMI since 2007.