You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).
Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.
Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM.
This training can either be delivered as a full 5-day course, or by attending two separate sessions, as detailed below:
Part 1: Essential VHDL Verification (3-day course)
You will learn to create structured transaction-based testbenches using either procedures or models (aka: verification IP or transaction level models). Both of these methods facilitate creation of simple, powerful, and readable tests.
Part 2: Expert VHDL Verification (2-day course)
Building on the core topics covered in Essential VHDL Verification, Expert VHDL Verification teaches advanced topics including modeling multi-threaded models (such as AXI4-Lite), advanced functional coverage, advanced randomisation, creating data structures using protected types and access types, timing and execution, configurations and modeling RAM.
To ensure in-depth learning, 50% of the class time is devoted to hands-on exercises and labs. The lecture and labs contain numerous examples that can be used as templates to accelerate your test and testbench development.