Advanced VHDL Testbenches & Verification - FirstEDA
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Advanced VHDL Testbenches & Verification

INSTRUCTOR-LED TRAINING SERIES

Learn the latest VHDL Verification techniques and methodologies for FPGAs and ASICs, including the Open Source VHDL Verification Methodology (OSVVM).

You will gain the knowledge needed to improve your verification productivity and create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog (UVM).

 

Unlike UVM, our methodology works with any simulator that supports VHDL-2008, removing the requirement to learn a new language or invest in new and costly tools.

 

Developed and delivered by Jim Lewis, chair of the IEEE VHDL standards working group and chief architect of OSVVM. The training can either be delivered as a full 5-day course, or by attending two separate courses, as detailed below:

Part 1: Essential VHDL Verification (3-day course)

You will learn to create structured transaction-based testbenches using either procedures or models (aka: verification IP or transaction level models). Both of these methods facilitate creation of simple, powerful, and readable tests.

DISPLAY COURSE BENEFITS

  • Use OSVVM’s structure transaction base framework
  • Write OSVVM Verification IP
  • Simplify test writing using interface transactions (CpuRead, CpuWrite)
  • Add error injection to interface transactions
  • Implement a test plan that maximises reuse from RTL to core to system-level tests
  • Write directed, algorithmic, constrained random, and Intelligent Coverage random tests
  • Write Functional Coverage to track your test requirements (test plan)
  • Simplify error reporting using OSVVM’s Alert and Affirm utilities
  • Simplify conditional message printing (such as for debug) using OSVVM’s log utilities
  • Add self-checking to tests
  • Use OSVVM’s Generic Scoreboards and FIFOs
  • Use OSVVM’s Synchronisation Utilities (WaitForBarrier, WaitForClock, …)
  • Model analogue values and periodic waveforms
  • Utilise OSVVM’s growing library of Open Source Verification IP

Part 2: Expert VHDL Verification (2-day course)

Building on the core topics covered in Essential VHDL Verification, Expert VHDL Verification teaches advanced topics including modeling multi-threaded models (such as AXI4-Lite), advanced functional coverage, advanced randomisation, creating data structures using protected types and access types, timing and execution, configurations and modeling RAM.

DISPLAY COURSE BENEFITS

  • Write complex, multi-threaded verification components, such as AXI-Lite
  • Use configurations to control which test runs
  • Validate self-checking models
  • Write AXI Stream Master and Slave Models
  • Write models with interrupt handling capability
  • Simplify memory model implementation using OSVVM’s MemoryPkg,
  • Write protected types and access types
  • Understand VHDL’s execution and timing
  • Advanced Coverage and Randomisation techniques

To ensure in-depth learning, 50% of the class time is devoted to hands-on exercises and labs. The lecture and labs contain numerous examples that can be used as templates to accelerate your test and testbench development.

We were looking for verification methods, without having to learn a new language. This is it!”

Everyone should use this approach - even if not using this language.”

Jim is passionate about good verification.”