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Advanced Design Rule Checking / FPGA / FV / SAFETY / ASIC

ALINT-PRO is a design rule checking (DRC) tool. It uses rule files (‘policies’) to check that a design’s RTL adheres to a defined RTL coding style. It decreases development time dramatically by identifying design issues early in the development schedule.

ALINT_PRO provides configurable design rules that are based on industry standards such as STARC, DO-254 and other customer-derived requirements. It works in conjunction with the manual review process, and makes a valuable contribution to the overall design process when developing safety-critical applications (which must comply with standards such as IEC 61508 and DO-254/ED-80).

ALINT-PRO easily integrates into existing development environments.


ALINT-PRO’s main role is to identify design weaknesses before they manifest into bugs. It essentially provides the earliest level of verification, by checking your design against good coding practices.

  • Compile time analysis
  • Elaboration (structural) design analysis checks
  • Supports VHDL & Verilog
  • Phase-Based Linting (PBL) Methodology
  • Rule plug-ins based on industry standards such as STARC & RMM
  • Integrated result analysis and code tracing environment
  • HTML & text reporting
We are very aware that companies designing applications for FPGAs are constantly looking for ways to improve their development processes. Moreover, if the application is safety-critical – for use in the aerospace, defence or transport sector, for example – there is a need to demonstrate that a clearly defined design process has been followed.
The first step on this journey is design review and automation, with ALINT-PRO DRC. This works in conjunction with the manual review process to demonstrate that a defined design style has been followed. Automation ensures code analysis is run regularly, reducing risk by identifying errors early in the development process.