ISequenceSpec

AUTOMATICALLY GENERATE UVM SEQUENCES / ASIC D&V

ISequenceSpec enables users to describe the configuration, programming and test sequences of a device and automatically generate sequences that are ready to use during early verification stages, firmware development and post-silicon validation.

 

From a single sequence specification, you can generate UVM sequences for verification, C code for firmware and device driver development, SystemVerilog sequences for validation, and various outputs including CSV for Automatic Test Equipment.

A common Sequence specification serves as a powerful tool for stimulus generation used by multiple teams involved in verification, firmware and post-silicon validation stages. But most SoC teams lack a unified flow for creating sequences – each team has to manually write sequences in their formats, thus wasting time and resources.

 

ISequenceSpec auto-generates test and configuration sequences for custom IPs. Users can define the sequences in pseudo-code and retarget the sequences in various languages including UVM sequence for simulation, C for firmware tests and C/ASCII/CSV for post-silicon validation.

  • Sequence editor available in Word, Excel or Python text
  • Capture hierarchical sequences at a higher level in-sync with register specification
  • Sequence constructs include fork/join, constraints and randomisation, loops, if-else, wait, arguments, constants, in-line functions

Our customers challenged us to “do for sequences what we did for registers”. In creating ISequenceSpec, we used the lessons learnt from years of enhancing IDesignSpec. 

Features and Benefits

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  • Automate the generation of code for device initialisation and other important device sequences
  • Simple, natural, portable sequence format for multiple IP/cores and SoC
  • Capture sequences at a higher level in-sync with register specification
  • Use register descriptions in standard formats like IP-XACT, SystemRDL, RALF or leverage on IDesignSpec integrated flow to use register data
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  • System Verilog UVM sequences for verification
  • Verilog for validation
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  • Improves semiconductor design sequence, accuracy and test validity
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  • A single specification format ensures synchronisation between various stages
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  • Easy to use
  • Sequence constructs include loops, if-else, wait, arguments, constant, in-line functions etc.
  • Capability to compile, flatten and unroll the sequences
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  • Variety of formats for various Automatic Test Equipment
  • Documentation in HTML and other formats
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  • Saves time by automatically generating the test sequences
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  • Quickly run the verification and firmware tests in the lab
  • Quickly run the post silicon failure test cases in the simulation environment

Language Features and Properties
Sequences can be specified using a rich language and command feature set that includes loops, branch, wait, calls, switch, and macros. Several properties can also be defined for customising the generated outputs. These properties can be created by using explicit property name-value pair or using the curly bracket syntax in the description.

Sequence Syntax Checker
A number of semantic problems can occur during the development of a sequence. ISequenceSpec is equipped with a smart syntax and semantic checker for validating the format and syntax within the specification. The entire specification is validated and a report containing a complete list of all problems opens in a window for viewing with cross-navigation to the row containing the problem. The checks carried out by the validation process include:

  • Register Validation – guides you to the row containing the register problem
  • Syntax Validation – Sequence step validation is performed, which checks the existence

 

 

Availability
ISequenceSpec is available as s a plug-in for popular editors that are commonly used to document registers such as Microsoft Word, Microsoft Excel and OpenOffice/LibreOffice Cal on Windows and Linux platforms. It is also available as a Batch tool to run on the command line in a ‘Make’ based flow.

Licensing options for ISequenceSpec include the following:

  •   Floating LAN/WAN
  •   Site License

 

Related Articles, Blogs and Videos

PRESS RELEASE: Agnisys @ DVCON India 2019: Presenting the Latest Release of ISequenceSpec Sequence Generator for Custom IPs

ARTICLE: Sequence Generation with ISequenceSpec and Cadence Perspec

BLOG: Creating Test Sequences for RISC-V Cores and SoCs

BLOG: Setting the Stage for the Next Abstraction

 

 

Ian Gibbins Ian Gibbins, Applications Specialist, FirstEDA

“ISequenceSpec saves engineers time by automatically generating test sequences which are then ready to use during early verification stages, firmware development and post-silicon validation. The tool is easy to use and it improves semiconductor design sequence, accuracy and test validity. ISequenceSpec ensures a single specification format between all teams and keeps each design team member aligned with the updated sequences and functionality as the project progresses, saving time and resources.”

Contact us for more information and pricing.