Blog: Assertions in Aldec Riviera-PRO
Blog: Riviera-PRO as a Register Generator Tool ...
19 December, 2022
Archive
Blog: Riviera-PRO as a Register Generator Tool
Blog: Riviera-PRO as a Register Generator Tool ...
13 December, 2021
Blog: Automation in UVM Register Modelling
In this blog, Nomita provides insight into communications between hardware and software for UVM verification engineering....
20 July, 2020
Blog: Agnisys Blog Post – Repurposing von Neumann Architecture with SRAM-based Register Files
The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big data the...
03 January, 2020
Blog: Agnisys Blog Post – Register Automation using Machine Learning
Can we accurately predict the register description (architecture, data flow, register name, field size, default value, offset and access type) by identifying patterns in plain...
29 November, 2019
Blog: Agnisys Blog Post – Setting the Stage for the Next Abstraction
Abstraction has been the key tool that helped us manage and reduce the problem space over the years, and once again we need it to...
29 November, 2019
Blog: Agnisys Blog Post – Creating Test Sequences for RISC-V Cores and SoCs
Louie De Luna discusses creating test sequences for RISC-V cores and SoCs...
11 November, 2019
Blog: Aldec Blog Post – Problems Accessing Registers? – See how UVM RAL can help.
Sunil Sahoo, Corporate Applications Engineer for Aldec, discusses the problems facing accessing registers, and how UVM RAL can help....
09 August, 2019