Archive
Connecting Emulated Design to External PCI Express Device
Connecting Emulated Design to External PCI Express Device...
02 June, 2020
When is robustness verification for DO-254 projects complete?
When is robustness verification for DO-254 projects complete?...
02 June, 2020
Correct-By-Construction SystemVerilog UVM Testbenches
Modern RTL design verification (DV) environments are both very powerful and very complex....
02 June, 2020
Aldec’s New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the ‘Price/Performance’ Sweet Spot
Aldec’s New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the ‘Price/Performance’ Sweet Spot...
05 May, 2020
GapFree Processor Verification
Tom Anderson, OneSpin Solutions Applying formal verification to thoroughly verify a RISC-V processor design. Not so long ago, many semiconductor and system suppliers developed their own processors,...
03 April, 2020
Mark Christiaens, Head of Engineering Sigasi
Mark Christiaens, Head of Engineering Sigasi...
31 March, 2020
The consumer revolution over the past few decades has funnelled a growth of SoC chips primarily in the area of consumer electronics.
The consumer revolution over the past few decades has funnelled a growth of SoC chips primarily in the area of consumer electronics....
24 March, 2020
Michelle Mata is an Applications Engineer at Aldec focusing on Hardware Emulation Solutions. She received her B.S. in Computer Engineering from the University of Nevada, Las Vegas in 2018.
Michelle Mata is an Applications Engineer at Aldec focusing on Hardware Emulation Solutions. She received her B.S. in Computer Engineering from the University of Nevada,...
20 March, 2020
We are pleased to announce that Aldec’s flagship RTL simulator Riviera-PRO now supports SweRV!
We are pleased to announce that Aldec's flagship RTL simulator Riviera-PRO now supports SweRV! The makefile that includes Riviera-PRO has now been merged into the...
18 March, 2020