Archive
Introduction: The Challenges of Verifying RISC-V
Introduction: The Challenges of Verifying RISC-V ...
04 June, 2020
cocotb: Use Python and bring joy back to verification
cocotb: Use Python and bring joy back to verification...
02 June, 2020
Global STAC Live
Sigasi is joining the Global STAC Live online event. Come and visit their virtual booth!...
02 June, 2020
How to develop high-performance deep neural network object detection/recognition applications for FPGA-based edge devices
Faster inference in DNN-based applications using FPGAs ...
02 June, 2020
Connecting Emulated Design to External PCI Express Device
Connecting Emulated Design to External PCI Express Device...
02 June, 2020
When is robustness verification for DO-254 projects complete?
When is robustness verification for DO-254 projects complete?...
02 June, 2020
Correct-By-Construction SystemVerilog UVM Testbenches
Modern RTL design verification (DV) environments are both very powerful and very complex....
02 June, 2020
Aldec’s New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the ‘Price/Performance’ Sweet Spot
Aldec’s New HES FPGA Accelerator Board Targets HPC, HFT and Prototyping Applications plus Hits the ‘Price/Performance’ Sweet Spot...
05 May, 2020