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02 December, 2021
Archive
Live Webinar: Boost VHDL Development Time with Background Design Rule Checking
Design rule checking (DRC) is a battle-proven method to improve the quality of digital designs. In safety-critical design processes, such as DO-254, applying design rule...
24 November, 2017
Event: NMI FPGA Network – Safety, Certification & Security – 19 May 2016, Hatfield UK
[vc_row][vc_column width="1/6"][vc_single_image image="21916" border_color="grey" img_link_large="" img_link_target="_self" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]FPGA Network: Join NMI’s Safety, Security & Certification FPGA Meet on 19th May along with delegates from Abaco...
16 May, 2016
Live Webinar: Fast Track to ALINT-PRO – Design Entry and Linting
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]This “Fast Track” series webinar is designed to help engineers get up to speed quickly with ALINT-PRO. Learn how...
17 November, 2015
Live Webinar: DO-254 – How to Formulate an Efficient PHAC
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]Randall Fulton, FAA DO-254 DER, will share his industry insights from 18 years of holding approval authority for PLDs ...
06 October, 2015
Live Webinar: Go with the Flow
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]Chris Higgs of Potential Ventures will demonstrate what is arguably the most productive RTL development flow in the world ...
14 July, 2015
Live Webinar: FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms — THURSDAY 9 JULY - 14:00-15:00 BST (15:00-16:00 CEST) Presented by...
07 July, 2015
Live Webinar: The elusive systemic error – equivalence checking for your FPGA
[vc_row][vc_column width="1/6"][vc_single_image image="21937" border_color="grey" img_link_large="" img_link_target="_self"][vc_column_text]Alex Grove FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]Discover why designs teams are increasingly seeing the value of running equivalence checking during FPGA development to rapidly...
29 June, 2015
Blog: The case for running equivalence checking on your FPGA
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="21937" qode_css_animation=""][vc_column_text]Alex Grove FirstEDA[/vc_column_text][/vc_column][vc_column width="5/6"][vc_column_text]Why we should continue to leverage ASIC methodology solutions during FPGA development — A few...
25 June, 2015
Live Webinar: OSVVM for VHDL Testbenches
[vc_row][vc_column width="1/6"][vc_single_image image="18721" border_color="grey" img_link_large="" img_link_target="_self"][/vc_column][vc_column width="5/6"][vc_column_text]With Intelligent Coverage, OSVVM offers a built-in VHDL-based, testbench solution. Best of all, OSVVM is free and works in all...
24 June, 2015