A Hardware Emulation Guide for Non-C Designers
Blog by Jacek Majkowski, Senior Hardware Engineer
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The two questions I hear most often while doing presentations about SCE-MI transaction based emulation are “Can we have coffee break?” and “Why do we need a thin C layer between two SystemVerilog tops”?
You are probably reading this during a coffee break, so let’s jump to the second question. It refers to this diagram showing how to connect a SystemVerilog testbench (usually UVM) with DUT in SystemVerilog using a DPI transactor, as defined by the Function-based Interface of SCE-MI.
There are two main reasons for this. First, the SCE-MI standard was designed with the assumption that a testbench will use C/C++ modelling environment such as SystemC. Second, DPI (SystemVerilog Direct Programming Interface) was designed as inter-language communication mechanism based on function calls, so the user can define function in one language (C or SV) and call it from another (SV or C). So to use the DPI interface between the SV testbench and SV DUT it is necessary to use thin C layer.
Fortunately if you are allergic to even a bit of C code, here are three options to avoid writing it.