Insight: Exploring An Open Source Risc-V Core

By Hendrik Eeckhaut

 

This weekend I read that Western Digital published the (System)Verilog sources of their Open Source Risc-V core on GitHub. Of course I wanted to try how easy it was to import this project in Sigasi Studio and test how well Sigasi Studio handles this code base.

 

I started by cloning the project….