June 18th, 2019
Henderson, NV – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has introduced automatic UVM register generation to Riviera-PRO, the company’s advanced verification platform. Accepting a CSV file or IP-XACT register description as an input, Riviera-PRO will, working at the Register Abstraction Layer (RAL) of UVM, output files as RTL register models, C headers and HTML.
In addition, libraries containing pre-compiled source code compliant with the latest versions of UVM (IEEE 1800.2-2107) and UVVM (2018.12.03), plus documentation and examples, have been added to Riviera-PRO to facilitate easier and better test bench creation.