June 3rd, 2019
DAC 2019, Las Vegas, NV – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has developed a high-speed HDL synthesiser called SyntHESer as a part of the company’s HES-DVM emulation tool. Accordingly, users of HES-DVM can be spared from investing money in, and time integrating, a third-party synthesiser.
As for performance, in a recent in-house bench test SyntHESer performed 10x faster than a leading standalone synthesis tool when handling identical blocks of HDL for a circa 45-million-gate Deep Learning Accelerator (NVDLA) design. Multiple synthesis jobs can be run concurrently on HES-DVM, and for the NVDLA design SyntHESer took less than 20 minutes to synthesise the HDL.