Aldec to Highlight ASIC Pre-Silicon Verification Spectrum with Network-On-Chip (NoC) Demonstration at DVCon Europe
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Aldec announced today that they will present the spectrum of pre-silicon verification solutions at the DVCon Europe Conference and Exhibition to be held October 19-20, 2016 in Munich, Germany.
At DVCon Europe, Aldec will demonstrate industry-proven verification methodologies and solutions using a Network-on-Chip (NoC) design based on research conducted at Stanford University by Daniel Ulf Becker. “The NoC was built as a mesh topology with a configurable number of routers that provide device connection nodes,” illustrates Krzysztof Szczur, Aldec Hardware Verification Products Manager. “The network is able to transfer data packets between any pair of nodes and therefore can serve as the backbone of a complex System-on-Chip (SoC) ASIC design.”