Aldec Sets a New Paradigm with a Single Platform for Design Rule Checking and Clock Domain Crossing Verification for FPGA and ASIC Designs
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Aldec announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017.01, a unified framework for static rule-based verification of VHDL and Verilog/SystemVerilog RTL designs targeting FPGAs and ASICs.
“Designers cannot afford to have repetitive RTL coding mistakes slipping through undetected to the very late stages of the design cycle,” said Sergei Zaychenko, Aldec Software Product Manager. “The latest release of ALINT-PRO helps designers and managers ensure a methodical use of design rule checking and CDC verification within a single platform, to uncover hidden bugs and confine non-deterministic defects the same day they were introduced into the design.”