Aldec Introduces Hybrid Emulation with ARM® Fast Model Support
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Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification solutions for system and ASIC designs, is introducing Hybrid Emulation including support for ARM® Fast Models. Announcing their new and easy-to-use capability to link an SoC emulation hardware platform with a virtual platform, Aldec is enabling FPGAs and SystemC models to work together to provide greater productivity and reduce time-to-market for embedded software in today’s SoC projects.
The two major components at the heart of Hybrid Emulation are the HES-7™ platform from Aldec, and Fast Models from ARM®, each providing leading edge capability to the combined solution.
HES-7 is so named because it is Aldec’s seventh generation Hardware Emulation Solution, based upon Xilinx® FPGAs and fully integrated into Aldec’s Design Verification Manager (DVM). The HES‑DVM™ suite is available in configurations using Virtex-2000T or Ultrascale-440 devices, offering the largest FPGA resource available on a single board, and over one billion ASIC gates in multi-board configurations.