PR: Aldec’s “Hardware and Software Co-verification in Hybrid Simulation and Emulation Environment with QEMU” DVCon Europe tutorial to demonstrate how engineers can obtain a holistic view over their SoC design

Munich, Germany – October 22, 2018 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will present a tutorial entitled “Hardware and Software Co-verification in Hybrid HDL Simulation and Emulation Environment with QEMU” at the DVCon Europe Conference and Exhibition, to be held on October 24 and 25, 2018 in Munich, Germany.

Tutorial: Hardware and Software Co-verification in Hybrid HDL Simulation and Emulation Environment with QEMU

Schedule: Wednesday, October 24, 4:00PM-5:30PM, Forum 5

Speakers: Radosław Nawrot, Aldec Inc. and Krzysztof Szczur, Aldec Inc.