PR: Aldec to Present Software Driven Test of FPGA Prototype
Aldec announced today that they will present “Tutorial: Software Driven Test of FPGA Prototype” at the DVCon Europe Conference and Exhibition to be held on...
11 October, 2017
Archive
PR: Formal Verification Leader OneSpin Solutions Unveils its Comprehensive Safety Critical Solution for Automotive, Other Mission-Critical
[vc_row css_animation="" row_type="row" use_row_as_full_screen_section="no" type="full_width" angled_section="no" text_align="left" background_image_as_pattern="without_pattern"][vc_column width="1/6"][vc_single_image image="22218" qode_css_animation=""][/vc_column][vc_column width="5/6"][vc_column_text]Random Fault Verification Supported by New Safety Critical Apps, Certification Kits — OneSpin® Solutions, provider...
13 June, 2017
Article: Jim Hogan rates all the EDA vendors on Safety Critical IC design
Hi, John, Today there is no one EDA company that has all the tools necessary to do safety critical chip verification (SCV), though virtually all are rushing to...
13 June, 2017
Article: Jim Hogan on using Formal along with random fault verification
Hi, John, Now it's time to discuss the second, much more complicated aspect of testing safety critical chips: random fault verification. This is needed because even if...
12 June, 2017
Article: CEO Interview – Stanley Hyduke, founder and CEO of Aldec
Dr. Stanley Hyduke, founder and CEO of Aldec talks about how keeping pace with the evolution of FPGAs and listening to customers underpin the company’s...
11 June, 2017
Article: Jim Hogan on ISO 26262 certification and systematic verification
Hi, John, Now let's look more closely at the ISO 26262 standard, the certification process, and how safety critical verification is split into analyzing systematic faults and random...
11 June, 2017
Article: Jim Hogan on how Safety Critical Verification is Next Big Thing
Hi, John, Since DAC'17 is only 3 weeks away, I thought I'd expand on my past DeepChip series related to verification [Formal, COVE, Emulation], and on my...
10 June, 2017
OSVVM: Making VHDL transaction-based testbenches simple, readable and powerful
Just because your design is complex does not mean your testbench needs to be. In OSVVM we have found that with proper abstractions we can...
07 June, 2017
Article: Why Auto Designs Take so Long
Designing chips for the automotive market is adding significant overhead, particularly for chips with stringent safety requirements....
06 March, 2017
Job opening: Sales Engineer (HES)
Continued success is driving growth and territory expansion. We are seeking a Sales Engineer, with a background in digital ASIC/FPGA design, specifically to support our...
22 February, 2017