Blog: OSVVM, a VHDL verification methodology that is easy to adopt

If you are a verification engineer, then it is pretty likely that you will either already be using or be looking into verification methodologies that address today’s challenges. These challenges allow re-use, add robustness to your stimulus generation and are fit for testing today’s complex designs.

I have worked in design and verification myself for many years and have seen quite an alarming shift in verification methodologies used to test FPGAs these days. On the one hand, I have witnessed many aerospace companies using ‘old-fashioned’ directed tests for testing their safety-critical FPGA’s, and on the other, modern VHDL based FPGA design companies going out of their way to adopt SystemVerilog and UVM for verification, despite its overheads. UVM has been in the ASIC world for a long time, where its use is justified given that ASIC re-spin is very costly. In my opinion however, UVM is overkill for verifying FPGAs and I would instead be looking for some sort of middle-ground.

When looking into different verification options some time ago, I came across the Open Source VHDL Verification Methodology (OSVVM), architected by Jim Lewis. Although I’d always intended to learn more about OSVVM, it wasn’t until I joined FirstEDA as an Applications Specialist that I was fortunate enough to learn from Jim Lewis himself, by attending the online Advanced VHDL Testbenches & Verification training that FirstEDA deliver in partnership with Jim’s company SynthWorks.

Learning first-hand from Jim was an inspiring experience and from joining his classes each day, I gradually realised the benefits of this methodology. To my surprise, I found that it offers more than I had hoped from a ‘middle-ground approach’. Besides being free and open-source, it offers SystemVerilog and UVM-like benefits and is easy to adopt without the need to retrain VHDL engineers to learn a very different language. It is comprehensive, and from the implementation of functional coverage to coverage randomisation, transcripts and alerts, and the support for intelligent coverage, it is now easy to achieve 100% functional coverage in less time than ever before. Hence companies can now easily create self-checking testbenches and drastically reduce FPGA development time by adopting this methodology. If only I had learned about OSVVM when working as a design and verification engineer!

OSVVM has an established and growing community of users, who you can connect with and discuss your challenges in the forum at osvvm.org. Here you will find a wealth of information and resources about the methodology and it’s packages. Being open-source, there’s nothing stopping you from using OSVVM straight away. However, if like me you want to learn how to get the most out of OSVVM and how to deploy the methodology most effectively, then I encourage you to also consider our Advanced VHDL Testbenches & Verification online training. Details of which can be found on the FirstEDA website here.