Newsletter 2020 Q2

In this newsletter, you will find articles about the basic differences between Paged registers and Alternate register, Auto-Mirroring for volatile registers, Clock Domain Crossing synchronization in IDesignSpec and smart assembly of SoC designs. Wish you and your families a safe and healthy future.



Auto-Mirroring for Volatile Registers
UVM Register Abstraction Layer (RAL) is a high-level object-oriented abstraction layer to access the registers in a design. The RAL model mimics the design registers and this allows the verification team to ensure correctness of the design. UVM RAL supports different register access like R/W, RO, WO, W1C, etc. from the CPU bus (we call it the software side). In addition, there is access from the application logic for which the design is being built (we call it the hardware side). The same model can be accessed by multiple software side buses. When a hardware event occurs in the design, the registers can be updated as a result. Such registers are called volatile registers. For example, a register can indicate the state of the application logic which is read by the CPU – hardware access is write-only, and software access is read-only. The value from the design (RTL) will not be mimicked on the RAL model on its own; something needs to be done. To overcome this shortcoming in the UVM RAL, we use a technique called auto-mirror. This article discusses how we handle it in IDesignSpec™. Read more