FPGAs for Verification, UVM Simulation Acceleration with Scalable FPGA Platforms
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THURSDAY 9 JULY – 14:00-15:00 BST (15:00-16:00 CEST)
Presented by Alex Grove, FirstEDA Applications Specialist
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Most ASIC IP and SoC platforms will be validated at some point using FPGAs; this task is typically referred to as ASIC FPGA prototyping. At the same time, FPGAs are increasingly being used for verification due to the performance and scalability of these systems.
In this webinar we will introduce an approach whereby UVM tests can be accelerated with the use of an FPGA co-emulator. The approach is built upon industry standards SystemVerilog and SCE-MI, and requires no changes to the test environment to accelerate. This enables tests to be moved seamlessly from simulation to the accelerator and back again.