Modern integrated circuits (ICs) provide the computational and system control capabilities to process enormous amounts of data, make safety-critical decisions in real time, and protect sensitive data.
Designing an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA) system-on-chip (SoC) from scratch would be prohibitively expensive and time-consuming. Many critical functions are implemented using third-party intellectual properties (IPs). Processor cores, for example, are sourced from specialized organizations and provide a flexible, software-programmable function through their instruction set architecture (ISA), which defines the interface between hardware and software. Open-source processor architectures provide an opportunity for deeper scrutiny and rigorous security assurance in systems that are already facing a fluid threat environment. This article describes an approach for providing security assurance of IP and SoCs based on the RISC-V open-source ISA.
Invented at the University of California and managed by the non-profit RISC-V Foundation, RISC-V is the first open-source ISA to become a genuinely viable industrial choice for a broad range of applications.