Blog: Do you think in pictures?

David Clift

FirstEDA

We’re well into summer now and I am still working from my home office, which has its pros and cons!
—

As I look to the right of my desk, there is a bookshelf containing some interesting titles; “The Explosive Child” sits on the same shelf as “A Boy made of Blocks” and “Thinking in Pictures”. I must admit that these aren’t my books, but my wife’s, who is a speech and language therapist specialising in Autism. Books about electronics do not have such interesting titles, unless maybe you are reading “Bebop to the Boolean Boogie” by my old colleague Clive “Max” Maxfield. But the titles of my wife’s books, up there on the bookshelf, could so easily relate to electronics design.

When I first started designing in the era of Texas 74LS and CMOS 4000 IC’s, designs were realised on sheets of drawing paper. Starting with top-level block diagrams and then lower-level logic diagrams, drawn out with care using stencils, ruler and pencil. These early days of seeing my designs come to life as a line of graphite on the page mean that when today I think of circuit designs, they come to me as pictures of blocks containing registers and logic cells. I have now been using HDL’s for many years, but I still think in terms of pictures and rarely, if ever, in lines of code; Is this an affectation of my early electronics design experiences, or do today’s HDL centric engineers think in pictures or lines of Code? I do not know, go discuss…

As they say, “a picture is worth a thousand words” and even with today’s powerful HDL’s this is still true. When I create a new design I still start at the top and break it down into several interconnected blocks. This helps me decompose the problem down into manageable chunks. So in my mind, tools that can support this flow are essential and that’s one of the great things about Aldec’s Active-HDL. I can start a design by creating my top-level block diagram, just adding boxes and connecting them up. If I have code I want to re-use, I just compile it and add the auto-generated block to the design. Once I have finished, Active-HDL will generate VHDL, Verilog or even EDIF from my diagram ready for simulation.

In today’s HDL centric designs, it’s still an advantage to be able to think in pictures and even to draw them. Keep safe until the next time.