A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key building blocks for the simulation testbenches at the heart of the DV process. The previous post focused on correct-by-construction of UVM testbenches using the DVinsight™ smart editor from Agnisys. This post shows how other solutions from Agnisys can automate the generation of the UVM Register Abstraction Layer (RAL) that provides testbench access to the registers and memories in the design being verified.
The UVM uses object-oriented techniques to provide a set of base class libraries that can be extended for use across a wide range of DV projects. The UVM RAL provides a standard library of base classes and methods with a set of rules to reduce the effort required for register access from testbenches. The RAL classes are used to create a high-level, object-oriented model for memory-mapped registers and memories in the design under verification (DUV). The UVM RAL provides a high-level abstraction for reading and writing DUV registers using user-defined names. It provides a register test sequence library containing predefined test cases these can be used to verify the DUV registers and memories. The registers and memories can be accessed via the RTL design’s bus interface, or independently by calling read/write methods.