February 28th, 2019 – By: Brian Bailey
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
The open-source RISC-V instruction set architecture (ISA) continues to gain momentum, but the flexibility of RISC-V creates a problem—how do you know if a RISC-V implementation fits basic standards and can play well with other implementations so they all can run the same ecosystem? In addition, how do you ensure that ecosystem development works for all implementations and that all cores that claim to be RISC-V have implemented the specification correctly?