Article: Mitigating Risk Through Verification - FirstEDA
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Article: Mitigating Risk Through Verification

Automatic coverage model generation technology continues to advance.

 

Verification is all about mitigating risk, and one of the growing issues alongside of increasing complexity and new architectures is coverage.

The whole notion of coverage is making sure a chip will work as designed. That requires determining the effectiveness of the simulation tests that stimulate it, and its effectiveness in terms of activating structures of functional behavior and design.

 

December 5th, 2018 – By: Ed Sperling