Article: Developing Robust Finite State Machines Code With Lint Tools - FirstEDA
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Article: Developing Robust Finite State Machines Code With Lint Tools

November 26th, 2019 – By: Alex Gnusin

 

Revealing finite state machine design bugs at the earliest stages of code development.

 

As design size and complexity grows, the design verification effort grows even more. It takes significant amount of time to thoroughly verify complex control logic of a design, which is the key and the most critical component of design functionality. One of the most common design patterns in the control logic design are finite state machines. They could be designed in different styles, state and output logic encodings, being either complex or simple for design, maintenance and verification. It is important to use the “Design-for-Verification” approach to develop Finite State Machines in a concise, robust and easy-to-verify way.

 

RTL code linting is the well-known approach ensuring design to be compliant with the collection of industry-best design guidelines for hardware development. Moreover, linting is able to automatically extract Finite State Machines structures from the design code and reveals FSM design bugs at the earliest stages of code development.