Article: Chiplet Momentum Builds, Despite Tradeoffs - FirstEDA
portfolio_page-template-default,single,single-portfolio_page,postid-23002,ajax_fade,page_not_loaded,,qode-child-theme-ver-1.0.0,qode-theme-ver-14.5,qode-theme-bridge,wpb-js-composer js-comp-ver-6.2.0,vc_responsive

Article: Chiplet Momentum Builds, Despite Tradeoffs

May 13th, 2019 – By: Brian Bailey


Chip design is a series of tradeoffs. Some are technical, others are related to cost, competitive features or legal restrictions. But with the nascent ‘chiplet’ market, many of the established balance points are significantly altered, depending on market segments and ecosystem readiness.


Chiplets provide an alternative mechanism for integrating intellectual property (IP) blocks into a semiconductor device. An IP block contains a prepackaged function that has been through several stages of design and verification. Traditionally, IP blocks were designed or purchased, and then integrated onto a single monolithic chip, which was then mounted into a package. With chiplets, multiple discrete die, each containing a purchased piece of IP, are integrated within a package using package-level interconnect. This process often is referred to as 2.5D or 3D integration, heterogeneous integration, or systems-in-package.