November 18-21, Denver Colorado
Booth #228, Aldec Inc.
We will showcase the recently introduced automatic FPGA partitioning feature of our popular HES-DVM tool, our fully automated and scalable hybrid verification environment for large SoC designs. Manual partitioning of designs with multiple FPGAs, can take days or even weeks, whereas HES-DVM can perform the task in minutes.
The partitioning software can be used with Aldec’s HES Prototyping boards and as well as 3rd party prototyping boards.