VHDL 2018 Support & Enhanced Automation - Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO - FirstEDA
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VHDL 2018 Support & Enhanced Automation – Aldec adds VHDL Standard 1076-2018 extensions and automatic coverage model generation to Riviera-PRO

Henderson, NV – November 13th, 2018 – Aldec, Inc., an industry leader in electronic design verification, has added VHDL-2018 interfaces and automatic coverage model generation to its Riviera-PRO™ advanced verification platform.

 

This early support for VHDL Standard 1076-2018 includes conditional compilations, conditional expressions in declarations, constraint inferral (from initial values), and bidirectional connections.